Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. The semiconductor memory devices include a plurality of memory cells, which also may be referred to herein as cells, each of which may exist in a plurality of memory states, which also may be referred to herein as states, illustrative, non-exclusive examples of which include a logic-0 state and a logic-1 state.
Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell is scaled to smaller feature sizes, difficulties arise due to the need to maintain the capacitance of the capacitor.
DRAM based on the electrically floating body effect has been proposed (see, for example, “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in conventional 1T/1C memory cells, and thus is easier to scale to smaller feature sizes. In addition, such memory provides for a smaller cell size compared to the conventional 1T/1C memory cell. However, unlike SRAM, such DRAM memory cells still require a refresh operation, since the stored charge leaks over time.
A conventional DRAM refresh operation involves reading the state of the memory cell, followed by re-writing the memory cell with the same data. This read-then-write refresh requires two operations: a read operation and a write operation. The memory state of the memory cell cannot be accessed while being refreshed. An “automatic refresh” method, which does not require first reading the memory cell state, has been described in Fazan et al., U.S. Pat. No. 7,170,807 and in “Autonomous Refresh of Floating Body Cell (FBC), T. Ohsawa et al., pp. 801-804, Tech. Digest, 2008 IEEE International Electron Devices Meeting. However, the automatic refresh operation still interrupts access to the memory cells being refreshed.
In addition, a maximum charge that may be stored in a floating body DRAM memory cell decreases with repeated read operations, leading to a decrease in a voltage difference among the plurality of memory states available to the DRAM memory cell and degraded cell performance. This reduction in floating body charge may be due to charge pumping, where the floating body charge is attracted to the surface and trapped at the interface (see for example “Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs”, S. Okhonin, et al., pp. 279-281, IEEE Electron Device Letters, vol. 23, no. 5, May 2002).
SRAM memory cells typically consist of six transistors (6T) and hence have a large cell size when compared to DRAM. However, unlike DRAM, SRAM does not require periodic refresh operations to maintain its memory state. Aside from the large cell size, 6T-SRAM also suffers from random threshold voltage (Vt) mismatches among its transistors, and requires a very complex custom manufacturing process for deep submicron IC fabrication.
Some electronic applications require the use of dual-port memory, which is a memory device that has two independent ports; each of which may perform the read and/or the write function. Existing dual-port memories use SRAM technology, such as in the 8T and 10T dual-port SRAM described by Chang, et al., US Patent Application Publication No. US 2007/0242513, and suffer from the same large cell size and random Vt mismatch problems as in single-port SRAM. Existing dual-port SRAM cell size is more than twice that of single-port SRAM cell size, and the dual-port SRAM cell also has a more complex overhead circuitry.
Another specialized memory type that is very commonly used is first-in first-out (FIFO) memory. FIFOs usually utilize dual-port SRAM and suffer from the same issues that SRAM memory cells suffer from, as mentioned above.
Dual-port memory utilizing the floating body effect has been proposed, for example, in U.S. Pat. No. 7,085,156 “Semiconductor Memory Device and Method of Operating Same”, R. Ferrant et al., and in U.S. Pat. No. 7,285,832 “Multiport Single Transistor Bit Cell”, Hoefler et al. The memory cell is formed by sharing the floating body regions of multiple floating body DRAM cells and still requires the refresh operation, which interrupts access to the memory cell.
Thus there is a need for improved semiconductor memory devices and methods of operating such devices such that the states of the memory cells of the semiconductor memory device are maintained without interrupting memory cell access. There is also a need for improved semiconductor memory devices and methods of operating the same such that the states of the memory cells are not degraded with repeated read operations.
In addition, there is also a need for improved semiconductor memory devices and methods that decrease and/or avoid the use of difficult SRAM custom doping to overcome random Vt mismatches in deep submicron process technology.
Furthermore, there is also a need for improved dual-port and FIFO memories that satisfy the properties above and also have a smaller cell size when compared to the traditional 6T SRAM cell.